`timescale 1ns/1ns

module fdiv5_3_tb ();
    reg clk_in,rst;
    wire clk_out;


    fdiv5_3 fdiv5_3_tb(
        .clk_in(clk_in),
        .rst(rst),
        .clk_out(clk_out)
    );

    initial begin
        clk_in = 0;
        
        #10 rst = 0;
        #20 rst = 1;
        #30 rst = 0;

        #5000 $stop;
    end

    always begin
        #5 clk_in = ~clk_in;
    end
endmodule